Flash type ADCs (analog-to-digital converters) are well known for many years. A Flash ADC is a type of that uses a linear voltage ladder with a comparator at each tap of the ladder to compare the input voltage to successive reference voltages. Often these reference ladders are constructed of many resistors, or alternatively, from many capacitors. The output of these comparators is generally fed into a digital encoder which converts the inputs into a binary value.
Flash converters are extremely fast compared to many other types of ADCs which usually narrow in on the correct answer over a series of stages. Compared to these, a Flash converter is also quite simple and, apart from the analog comparators, only requires logic for the final conversion to binary.
A Flash converter requires a huge number of comparators compared to other ADCs, especially as the precision increases. A Flash converter requires 2n-1 comparators for an n-bit conversion. The size and cost of all those comparators makes Flash converters generally impractical for precisions much greater than 8 bits (255 comparators).
The standard implementation of a flash ADCs (see FIG. 1) consist of a reference ladder of well-matched resistors 22, 24, 26, 28, 30 connected to a reference voltage. Each tap at the resistor ladder is used for one comparator 40, 42, 44, 46, 48, 50, possibly preceded by an amplification stage 32, 34, 36, 38, and thus generates a logical ‘0’ or ‘I’ depending if the measured voltage is above or below the reference voltage of the resistor tap. The flash ADC comprises two bubble error correction mechanisms 52, 54 as known in the art. The reason to add an amplifier is twofold: it amplifies the voltage difference and therefore suppresses the comparator offset, and the kick-back noise of the comparator towards the reference ladder is also strongly suppressed. Typically designs from 4-bit up to 7-bit are produced.
A drawback of the state of the art design is that the comparators must work with low signal level. Due to this problem, in many designs an amplifier is placed to amplify the difference between the input signal and the reference voltage. In order to reach high gain and high bandwidth, its power consumption is high. Since many of these amplifiers are present, the power consumption of this circuit is very high. Another reason for the high power consumption of the conventional design is that the ladder has to present low impedance otherwise it is sensitive to noise, and as such it consumes a large amount of current. The resistors also consume a large chip area. The accuracy of the ADC is also limited by the offset of the comparators and of the differential amplifiers.
High gain amplifiers might be implemented as a series of amplifiers in cascade. Such arrangement is better operated in a pipeline; otherwise only low speed operation is possible. A pipeline of amplifiers is usually arranged in a sample & hold configuration, in which each amplifier is connected to a switch and a capacitor. The rate of this S&H is a limiting factor in ADC design, the S&H requires many modules and a high speed S&H is relatively inaccurate. Pipeline architecture may be used to implement high gain before the comparators in this invention, but also may be used in other applications.